eSilicon to cut costs of ASIC development for IoT, other markets
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
Blog Topics
3D and EDA need to make up for Moore’s Law, says Qualcomm
Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase.
Remember 20nm? Qualcomm does
Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC's 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.
Chipmaking’s future: all of the nodes all of the time
The stall in Moore's Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.
Real Intent’s Pranav Ashar on converging design and verification
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
Samsung certifies Synopsys tools, IP at 14nm
Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Mentor’s Wally Rhines on tools as a cultural issue
Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
Synopsys uses virtual prototyping kits to kick start IP integration
Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
Post-silicon devices: maybe it’s in the way they move
A research-focused session at DAC 2014 looks at using coupled oscillators rather than charge transfer to process data.
Emulation ‘heart of ESL’
The emulator has become the cornerstone of embedded system level (ESL) design on SoC projects, analyst Gary Smith claimed in a speech ahead of DAC 51.
PLATINUM SPONSORS
View All Sponsors