IP

UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.

Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.

SureCore has started running 30-day trials of its low-power memory compiler.

IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.

Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.

Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.

This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.

Imagination Technologies has launched a new generation of GPU IP aimed at multitasking compute acceleration.

GlobalFoundries and TSMC have called off their legal battle with a wide-ranging patent cross-licensing deal.