IP partnership aims to crack down on physical hacks
UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
IP
CEVA splits vectors for more efficient 5G
CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.
DVCon US 2020 preview: SmartDV
The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
Debug connects with manufacturing test to cut product recall costs
UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.
Arm adds AI to Cortex-M cores
Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.
SureCore provides 30-day test for SRAM compiler
SureCore has started running 30-day trials of its low-power memory compiler.
MRAM pushes speed and endurance at IEDM
IEDM late last year showed how MRAM is being prepared for both FD-SOI and advanced finFET nodes.
Siemens and Arm combine to extend digital twin further into SoC design
Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm
Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
Support for RISC-V expands at summit
This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.