IP partnership aims to crack down on physical hacks

By Chris Edwards |  No Comments  |  Posted: April 16, 2020
Topics/Categories: Blog - IP  |  Tags: , , ,  | Organizations: ,

UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.

The aim is to combine analog monitors developed by Agile with the debug logic from UltraSoC to watch for attacks that use variations in power-supply voltages and temperature or which rely on clock glitches to prevent normal operation. Many of these attacks impair the ability of datapath and control logic to complete properly and have been used to escalate privileges on victim hardware. A common attack mode is to use sudden changes in voltage or clock rate to bypass verification checks. Others focus on rapid cooling to sub-zero temperatures in order to read memory contents more easily. A number of these attacks can be mounted with low-cost equipment. As more commercially sensitive systems are deployed at the edge and in the form of easily accessible IoT nodes, concern is growing as to their vulnerability to these physical attacks.

Agile Analog offers a range of monitoring IP cores that incorporate voltage, temperature, and timing sensors to watch for anomalous behavior that could indicate a cyber attack. Classical methods for dealing with these attacks tend to focus on quickly resetting the victim device and zeroing out session keys cached in memory. As part of an infrastructure built around the UltraSoC on-chip debug network, the IP can be used to provide warnings to system-level monitoring functions with more fine-grained control over responses to attacks.

Gajinder Panesar, CTO at UltraSoC, said: “Agile Analog has some unique technology that’s invaluable in monitoring the underlying analog behaviour of an SoC for potential signs of suspicious or unexpected activity. We believe that partnerships like this are key to enabling a holistic secure embedded cybersecurity architecture with monitoring capable of delivering from fab to field.”

Mike Hulse, CTO at Agile Analog, added: “Security is one of the key pain points faced by every electronics manufacturer today – particularly in industries such as automotive. The complementary nature of our technologies – UltraSoC offering system-level functional monitoring, and Agile Analog looking at underlying analog behavior – makes our products a natural fit for cybersecurity applications.”

UltraSoC embeds transaction-aware hardware monitors into the digital infrastructure of an SoC. These are interconnected via a message-based architecture, allowing the implementation of sophisticated system-wide anomaly detection and mitigation measures. The company has developed digital IP for security monitoring. The Bus Sentinel and CAN Sentinel hardware modules, for example, can identify and instantaneously block suspicious communications within the chip. According to UltraSoC, by integrating data from analog monitors developed by Agile, SoC integrators can develop a wider range of anomaly-detection schemes.

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