CEVA splits vectors for more efficient 5G

By Chris Edwards |  No Comments  |  Posted: March 4, 2020
Topics/Categories: Blog - IP  |  Tags: , , , ,  | Organizations:

CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.

The company designed the Gen4 CEVA-XC to be better at dealing with multiple parallel data and control streams to improve the utilization of the vector-accelerators the architecture deploys for signal processing. At a superficial level, the architecture has two eight-way very long instruction word (VLIW) processors. But the vector units are designed to be split in different ways to suit the needs of each task and improve overall silicon efficiency, in the expectation that the processor will be instantiated multiple times in an SoC.

“Maybe the biggest challenge in these applications is how to cope efficiently with multiple users and multiple tasks. This is a very challenging task to handle in a vector DSP,” said Nir Shapira, business development director at CEVA. “Also, in vector DSPs, typically what consumes the most area are the MAC units and the registers that go with them. It’s very important to make efficient use of those resources.”

The processors can be dynamically reconfigured as either a wide SIMD machine or divided into smaller simultaneous SIMD threads. The Gen4 CEVA-XC architecture also sports a 2048-bit wide memory cache-coherent interconnect to tightly coupled memory to support accesses from the two cores in parallel.

Each processor core has a scalar unit that can be allocated a number of slaves to form a vector-processing unit. “We have quad vector and dual vector modes and you can switch between these modes within a few cycles,” Shapira claimed. Typically, in systems where there is a large control overhead, the use of dual-vector modes on a collection of tasks results in a lower total cycle count for a given workload.

CEVA has developed constraints definitions and other EDA support scripts to ensure that the synthesizable core can be laid out on a 7nm process node and deliver its rated maximum clock speed of 1.8GHz. “This is a real number; not just a marketing target,” Shapira said.

The first processor based on the Gen4 CEVA-XC architecture is the multicore CEVA-XC16, aimed at Open RAN and baseband unit designs as well as high-end Wi-Fi and 5G enterprise access points. The company is working with lead customer already and expects general licensing to start in Q2 2020.

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