Breker adds automated system integration test generation for RISC-V
App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
IP
Imagination splits GPU lanes for high-utilization acceleration
Imagination Technologies has launched a new generation of GPU IP aimed at multitasking compute acceleration.
Foundries call off patent war
GlobalFoundries and TSMC have called off their legal battle with a wide-ranging patent cross-licensing deal.
DVCon Europe looks to software for next phase in verification
October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
Arm to let customers bolt instructions onto V8 processors
Arm has relented on its opposition to custom instructions with the decision to let customers add them to V8-M processors.
UltraSoC adds security checks to bus monitoring IP
UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.
Arm TechCon 2019 preview: Mentor
Mentor is active across the program at Arm TechCon with a range of conference and booth talks, demonstrations and presentations.
Accellera adds detail to proposed security assurance model
Accellera's security assurance working group has set out some of its plans in a white paper.
Ceva shares weights for lower DNN overhead
Ceva has employed a more extensive form of weight compression in its latest generation of DNN processor cores.
Synopsys claims 35TOPS performance from new family of embedded vision cores
IP core focuses on avodiing memory access bottlenecks during processing of complex machine-learning and artificial-intelligence algortihms.