IP

October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.

Arm has relented on its opposition to custom instructions with the decision to let customers add them to V8-M processors.

UltraSoC has developed a bus monitor that will terminate transactions if it detects behavior that breaks rules set by a system designer.

Mentor is active across the program at Arm TechCon with a range of conference and booth talks, demonstrations and presentations.

Accellera's security assurance working group has set out some of its plans in a white paper.

Ceva has employed a more extensive form of weight compression in its latest generation of DNN processor cores.

IP core focuses on avodiing memory access bottlenecks during processing of complex machine-learning and artificial-intelligence algortihms.

The digital-twin concept provides several avenues to achieving better safety analysis and is likely to benefit from Siemens' integration of Mentor activities.

DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.

Non-volatile alternatives to flash are finally moving out of the lab as Applied Materials launches production tools and Arm starts pushing MRAM.