VLIW


March 4, 2020

CEVA splits vectors for more efficient 5G

CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.
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January 7, 2019

Ceva extends control-oriented DSP

Ceva has followed its IoT-oriented Ceva-X series of processor cores with a more powerful family that is designed to handle control and signal-processing algorithms using the same pipeline.
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April 11, 2018

Tensilica DSP extends pipeline for performance

Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
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January 14, 2015

Cadence updates Xtensa with memory and power saving features

Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with changes for VLIW, power-saving caches and memory accesses.
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