In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.
The embedded FPGA is beginning to find a market, with communications leading the way but machine learning likely to drive further adoption.
FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.
After the moves by Cadence and Mentor, emulation in the cloud may only be the start of providing verification acceleration as a service.
Accellera has published the first release of the Portable Test and Stimulus Standard (PSS), with tools suppliers following up with software support.
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Panasonic and AIST have turned a resistive memory (RRAM) into a hydrogen sensor that they claim works at much lower energy than existing designs.
Despite the intense R&D going into storage-class and other novel forms of non-volatile memories, flash is set to continue as the bulk memory of choice, Micron executive claims in VLSI Symposia keynote.
What does it take to build data converter IP that will meet the reliability and functional safety requirements of the automotive industry?
Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
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