EDA

As well as starting up a version for the European market, the Accellera Systems Initiative is taking DVCon to India in the early autumn.

STMicroelectronics is using the OpenPDK standard from Si2 to speed up the production and delivery of process design kits (PDKs) and asks for wider adoption by foundries.

Any conference can only be as good as the feedback it gets. And next year's DAC team is actively looking for yours. It'll be worth your time.

Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.

Panel discusses Moore's law scaling beyond the 14nm node to 5nm, where economic, device, interconnect, materials, lithography and design issues abound

Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.

Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.

At DAC 2014, Intel’s chief security architect Ernie Brickell described the processor maker’s approach to protecting hardware and software from hacks and attacks.

Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase.