EDA

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.

Panel discusses Moore's law scaling beyond the 14nm node to 5nm, where economic, device, interconnect, materials, lithography and design issues abound

Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.

Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.

At DAC 2014, Intel’s chief security architect Ernie Brickell described the processor maker’s approach to protecting hardware and software from hacks and attacks.

Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase.

Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC's 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.

The stall in Moore's Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.

Verify early and simulate as little as possible - the idea is familiar but how do you get there?

Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.