EDA

GlobalFoundries has developed variants of the 28nm FD-SOI process that offer smaller die sizes and lower-power operation.

IBM, GlobalFoundries, Samsung and SUNY deserve kudos for manufacturing the first 7nm chip but the NREs involved still look frightening.

The leading EDA analyst passed away late last week after a short illness. Graham Bell offers this remembrance.

Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.

The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.

Foundry claims isolation and device integration advantages for 180nm SOI process, help to absorb extra costs of SOI wafers

The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.

Following Mentor's acquisition of Tanner EDA, management expect the integration will help with a drive into IoT applications and systems that need to go beyond standard IC lithography.

Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.

HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.