Chipmakers see 3x test-pattern saving in embedded-test logic

By Chris Edwards |  No Comments  |  Posted: June 30, 2015
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations: ,

Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using standard test generation and compression schemes.

A part of Mentor Graphics’ Tessent toolsuite, the embedded test-point technology provides a way to trade test cost for die area, in many cases letting chipmakers continue to use existing test equipment to process much higher-density SoCs. A paper by Broadcom, Mentor and the Poznan Institute of Technology expanded on initial results presented by Kamlesh Pandey, Broadcom associate technical director, at the U2U conference in April.

Issues such as the need for low-power ATPG and cell-aware size as well as sheer logic count have pushed the needs for compression to more than 200x, Pandey said, because the cost of adding scan channels to the 36 on existing tester equipment or increasing test time would push up overall chip cost. At 28nm, for Broadcom the compression target was a mere 40x.

SoC test pressure

At U2U, Pandey said: “16nm is where things started going out of control for traditional compression. The best compression we could see at chip level is 125x but we need 200x.”

Broadcom decided to put EDT to the test to see if it could close the gap by reducing the overall number of test patterns without losing test coverage, employing the technology in both launch-off-capture (LOC) and launch-off-shift (LOS) modes. In some cases, the pattern-count reduction compared to conventional ATPG was tenfold. Overall data volume also fell sharply.

The technique works by splitting logic cones during scan using additional logic gates that allow the inputs of gates fed from one signal under normal circumstance to receive different inputs during test. This allows one ATPG pattern to be used to test conditions that would formerly need two.

Steve Pateras, product marketing director for silicon test at Mentor, said the average pattern count reduction is “3.1x if you can afford a 1 per cent increase in die area”.

Use of the embedded test points is “a no-brainer for many companies”, claimed Pateras, . “It’s configurable. You can determine how many you want to put in. Tester time will often trump the small silicon area overhead. Even at the volumes in play today, for most customers it’s a good tradeoff.

“It’s configurable. You can determine how many test points you want to put in. Tester time will often trump the small silicon area overhead. Even at the volumes today for most customers it’s a good tradeoff,” Pateras said

Flow decisions

Test-point embedding is a gate-level technique that can be deployed before or after scan insertion – a decision that largely depends on the flow being used. However, Pateras said the plan is to make it possible to have EDT logic inserted at RTL to allow the test points to be optimized for physical synthesis in the same way as conventional logic so that critical paths can support the additional gates. Even at gate level, Pateras said implementation tools will often optimize placement enough to hide the delay of the test-point gates.

The tool can avoid highly critical logic paths, Pateras said: “You can tell it which patterns not to touch. You can limit the number of test points on a given path and make sure it is not used on clock-domain crossing paths or multicycle paths. There are a number of knobs that the user can use.”

Tuning of the tool is ongoing to further improve pattern reduction. “We’ve just increased its ability to reduce patterns by 10 per cent in the last release. It’s hard to say how far it could go.”

Hierarchical ATPG advantages

In parallel, Pateras said, “We’ve been improving our solution to improve automation for hierarchical flow. We are seeing some dramatic improvements in ATPG runtime and memory usage compared to a flat ATPG flow. That’s becoming a must-have when you get to much larger designs – ones that use 15 million or 20million gates.

“In those designs, it’s not feasible to to ATPG flat. It will take you weeks to do the patterns. We now have more than 20 customers doing hierarchical. There is very little cost to doing it, it’s just a flow issue. And it fits well with physical blocks [as they can follow the same hierarchy],” Pateras added.

“There is a huge scheduling improvement too. You can parallel things: you don’t have to get your whole design done before doing ATPG. You can do it when each core is ready and distribute the effort. From a resource optimisation point of view and scheduling it’s very beneficial. It’s a natural fit to how designs are evolving.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors