EDA

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold

Formal-verification specialist OneSpin is setting up its own equivalent of an app store, building on top of a formal engine the company now licenses to other companies.

Agnisys is adding automated verification of SoC register maps to its IDesignSpec tool for defining and specifying registers and their behaviours, deploying both a dynamic and a formal version.

Design and manufacturing services company draws on big data to offer ASIC block optimisations

Startup Tortuga Logic has developed a toolkit for checking the security aspects of SoC hardware designs.

Sonics is moving into power management with an approach intended to substantially automate much of the job of building finely grained power-gated SoCs.

As 2015's general chair for the Design Automation Conference, Anne Cirkel has looked to extend the attraction of the leading EDA, IP and embedded event.

May 19 is the deadline for 'I Love DAC' offering free access to exhibits and many events, panels and speeches at the 2015 Design Automation Conference.

Altera is revamping the Quartus II software for its FPGAs with a mapping and synthesis engine aimed at the upcoming Gen 10 products, as well as adding a C/C++ front-end for system-level design.

Intel 14nm finFET SoC process is among the highlights of the 2015 VLSI Symposia alongside research that looks at the integration of III-V and 2D materials for future processes.