FastSpice update improves parallelism and adds wreal support

By Chris Edwards |  No Comments  |  Posted: June 29, 2015
Topics/Categories: Blog - EDA  |  Tags: , , , , ,  | Organizations:

The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations. The 15.06 adds specific accelerations for circuits designed for BCD processes and support for real-number modeling.

Geoffrey Ying, director of analog and mixed-signal product marketing in Synopsys’ design group, said: “As processes move from bulk CMOS to finFET, the complexity really increases, particularly with respect to parasitics for post-layout simulation as well as in simulation for mixed-signal design. In finFETs the number of parasitics increased by five to ten times and it is very difficult to ignore these effects.

“Those increased parasitics put additional pressure on performance. Customers also now need to run many more corners. But the project schedule is the same.”

The issue with previous approaches to multithreading fastSpice simulations is that only some circuit types could take advantage of multiple processors. Others involved too many dependencies between calculations. A further issue was that the techniques were not necessarily thread-safe, leading to subtly different answers depending on the order in which the calculations across different processors were performed on a shared matrix.

Matrix split

The 15.06 update performs the division of work across processors in a different way that is more consistently amenable to multithreading – generally delivering speedups proportional to the square root of the number of processors used.

The inclusion of specific support for smartpower-oriented BCD processes such as those provided by STMicroelectronics follows on from the addition of a command specialized for SRAM simulation. The company expects to add more specific accelerations in the future.

“Not all designs are created the same. We made a conscious effort to do design-specific optimizations. First implementation of that was SRAM command. BCD is part two of that effort,” Ying said.

“Originally, fastSpice was created for CMOS. All the circuits within the design run at more or less the same voltage. So, in fastSpice, we do a lot of optimizations based on the fact that the supply voltage would be in that typical range. But a hundred volts and up are often needed in terms of voltage for BCD.

“We needed to create a new set of heuristics for BCD, primarily for handling the wide range of voltages. Also the partitioning optimizations had to be changed. So, we created a command for BCD where we could get roughly a 2x single-core speedup compared to the previous version of CustomSim.

Before, because of the wide range of voltages users had to us multiple commands were needed to tune the engine. Now, with the BCD command, it’s much easier to use,” Ying explained.

Real-number modeling

To support faster cosimulation with VCS in big-D, little-A designs, the latest version of CustomSim adds support for SystemVerilog’s netttype data type, a key component of real-number modeling (Guide).

Ying said: “Real-number modeling gives you a way to describe the analog portion of the design within a larger system and has become an important part of the development flow in mixed-signal verification. The nettype in SystemVerilog not only provides real number support but attaches multiple quantities to an element, as one quantity is not enough. You also need bidirectional support and the user-definable resolution of multiple drivers.”

The final major change for 15.06 is UPF support to make it easier to associate fastSpice simulations with the power state of a block within a larger SoC simulation.

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors