IMEC 5nm test chip to explore EUV and SAQP litho options
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
EDA
Expanding role of UVM takes center stage at DVCon Europe
Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.
Samsung taps Mentor tools for higher yielding close-loop DFM
Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
Vertical structures to debut at IEDM 2015
A novel approach to 3D NAND will be among the presentations at the International Electron Device Meeting to be held in Washington, DC in December.
Tanner EDA @ Mentor Graphics: Steady as she goes
Stability is the watchword as AMS and MEMS specialist Tanner retains much of its independence - a 'start-up with a billion-dollar company behind us'.
DVCon Europe initial technical program unveiled
DVCon Europe has published the technical program for its upcoming November conference in Munich, Germany.
Early registration opens for DVCon Europe 2015
Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
Flow exploration key to finFET network processor implementation
Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
10nm flow reveals complexity of finFET design process
Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
Samsung applies early prediction and color management to 10nm plans
Rapid virtual prototyping and a metal stack that's more designer friendly are two of the ways in which Samsung aims to build up foundry market share for its 14nm and 10nm finFET processes.