Samsung applies early prediction and color management to 10nm plans
Rapid virtual prototyping and a metal stack that’s more designer friendly are two of the ways in which Samsung aims to build up foundry market share for its 14nm and 10nm finFET processes.
In a designer track session at the recent Design Automation Conference, Kuang Kuo Lin, director of foundry marketing for Samsung US, described the company’s approach to dealing with the problems of achieving high power, performance and are (PPA) metrics on finFET processes, which are challenged by pin-access problems and difficult library choices.
Lin was keen to emphasize Samsung’s willingness to maintain a simpler migration to multiple patterning for both the 14nm and 10nm nodes, pointing to the choice of triple (LELELE) patterning for the lower metal layers, particularly metal one.
“We have a 2D M1 in 14nm and in 10nm,” Lin said, contrasting that approach with the self-aligned double patterning technologies that favor 1D routing. “We think that is a unique feature of our technology.”
“Samsung is slightly different to other foundries. We can take in colored or non-colored designs. And we do stitching to give better, easier color management,” Lin added.
Lin said custom designers will be able to control color for sensitive circuits in 10nm. “We have the ability to place the colour in the custom layout. For sensitive circuits you want matching, so you don’t let the tool touch the colour in the layout. For critical nets you can assign certain colors to make sure they are matched, such as SRAM bit cells.”
Samsung is also providing control over the way in which the fins are laid out. “You need to snap your fin to certain grids,” Lin said. “We allow the flexibility of local and global grids. The preference for either depends on different customers. Some prefer global, others local.”
To try to improve PPA and design for yield, Samsung has implemented a flow built around a series of short feedback loops that encourages early experimentation with different libraries and techniques.
“The traditional flow is a long loop. What we are trying to do is try to encapsulate all the things we need to do in layout in one framework. You do real-time, interactive DRC, LVS, DFM, dummy fill In one framework. And you can use a more systematic place and route system to facilitate design exploration.
“It’s a big decision to go from 28nm to finFET. There are different libraries with different PPA characteristics. How can you do a quick exploration? We try to make use of design-of-experiments system. You can create a pilot layout in different libraries. Nine or twelve-track, for example. You can plug in library collaterals and then do PPA analysis of different libraries and then compare the different technologies. Then use the scripts to tune the [actual] design flow.
“It’s one area where we are working with our design partners,” Lin added. “You can get very fast turnaround in a few weeks. You can come out with floorplans and look at scaling potential. You can tell your manager what are the PPA benefits of your technology.”
The early exploration allows analysis of the pin-accessibility constraints of different libraries for a given design and see how placement directives to provide more room for the detailed router affect congestion and area. “You can tune your process flow in this system and try to make sure that you take care of high pin count.”
Lin claimed Samsung’s ability to perform a fast ramp for finFET comes down to the company’s approach to DFM, “because of the DFM flow that we mandated. There is a table of mandatory and recommended requirements. We provide litho simulations for different patternings. [For smart dummy fill] we do correct-by-construction fill and color-correct fill.”
For custom design, Lin said the foundry service at Samsung has incorporated support for layout-dependent effects that supports early layout planning. “The layout-dependent effects are accentuated in finFET. There are lots of fin-to-fin, fin-to-poly-to-diffusion, and dummy-fin effects. Traditionally you had to wait for extraction and then send the results to the Spice model.
“We estimate there is 30 per cent time wasted if you do the traditional loop. You do a lot of design then wait for layout do post-layout simulation to look at the stress effects on neighboring devices.
“Today we incorporate information in models, whether local implant or stress effects. We encapsulate the models inside the custom layout to help tune the transistor or add a dummy. We are working with EDA partners to encapsulate the LDE models inside the tools. The model is very close to Spice, within 2 to 5 per cent,” Lin said.
Pingback: Flow exploration key to finFET implementation of network processor