Early registration has opened for the DVCon Europe conference to be held in Munich, Germany on the 11-12 November.
The conference is intended for system architects, concept engineers, software developers, design and verification engineers, and IP integrators to share the latest methodologies and technologies on the practical use of EDA and IP languages and standards used in electronic design and verification of embedded systems and integrated circuits.
The focus of this highly technical conference is on the industrial application of specialized design and verification languages such as SystemC, SystemVerilog, VHDL, UVM or e; assertions in SVA or PSL; the use of AMS languages; design automation using IP-XACT; and the use of general-purpose languages C and C++.
Early registration, available through 1 October, provides an approximately €100 discount off the normal pricing, with further discounts for Accellera members. The full conference registration provides access to the two-day conference and exhibition with lunch and the gala dinner on 11 November.