EDA

Talks in the Design-on-Cloud Pavilion at this year’s DAC demonstrated how the question over its usage is not so much whether design could or should migrate to the cloud but how to optimize cost and performance when it’s there.

DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday

Breker has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.

Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.

Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.

At DAC this week, Verifyter is offering a limited number of companies free six-month licences of its regression-analysis tool Pindown.

Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.

The organizers of DVCon Europe have decided to turn the autumn verification conference into a virtual event this year.

Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.