EDA

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.

Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.

The IEEE plans to stage the 66th International Electron Device Meeting as a physical event in mid-December.

DVCon US is to repeat sessions online from today until the middle of August, with exclusive access to registered attendees through early June.

Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.

A white paper details the parasitic extraction technology needed to help design high-performance RF SoCs.

Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.

Papers presented at the recent IRPS conference showed the growing importance of lifetime monitoring to the problem of handling components as they age.

Centaur opted for a superwide SIMD engine in an accelerator for a multicore x86 aimed at edge server applications that could take full advantage of spare die area.

Leading electronic system design conference confirms move online this July with Covid-19 restrictions and concerns expected to persist.