EDA

The Electronic System Design Alliance will discuss the benefits it offers for design and verification, and has added Avery Design Systems.

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.

Accellera has set up a working group with the aim of developing interoperability standards for functional safety.

By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.

The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.

Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.

Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.

Imec, TNO, and Cartamundi have developed a low-cost way of letting tags communicate with embedded devices wirelessly by using a capacitive touchscreen.

A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.