EDA

Speakers at this year's DVCon Europe called on the hardware community to find inspiration in software-development trends.

Functional verification for increasingly complex ARM-based designs is at the heart of the new consultancy partnership.

Among the papers that will be presented at the end of October, this year's DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.

As part of its move online during the pandemic, DVCon Europe is introducing what the organizers call Virtual Experience Rooms.

Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.

Small startup gets flexible cloud access to big iron to prove a novel processor architecture quickly.

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.

Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.

Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.

The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.