May 5, 2015
New version of Vivado adds verification features and speed, extends Zynq support
March 10, 2015
Synopsys claims its tools have enabled 90% of finFET designs currently going into volume production
February 3, 2015
Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
November 24, 2014
In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
October 24, 2014
Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates
October 14, 2014
Synopsys updates ARC core to improve support for embedded Linux and other advanced operating systems such as Android
October 8, 2014
DVCon Europe brings design and verification insights to Munich next week.
October 1, 2014
The Liberty library format has been extended to cope with the most common forms of on-chip variation analysis in use today on nanometer processes.
September 29, 2014
Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
September 29, 2014
TSMC has launched three processes the foundry is aiming at internet-of-things (IoT) and wearable-device designs, providing lower-leakage versions of its 55nm, 40nm and 28nm processes.