clock gating

May 24, 2018

Case study demonstrates 59% extra power savings for HPC

Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail
Article  |  Topics: Digital/analog implementation, Blog - EDA, - HPC, RTL  |  Tags: , ,   |  Organizations: ,
November 24, 2014

A57 finFET design underlines routing challenges

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
August 23, 2012

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
May 29, 2012

DAC 2012: Atrenta to automate production of power-intent constraints

Atrenta is updating existing tools and planning new ones to help designers get the most bang for their joule.
Article  |  Topics: Commentary, Conferences  |  Tags: , , , , ,   |  Organizations:
May 29, 2012

DAC 2012: Calypto brings tools together for high-level power savings

Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.


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