January 10, 2017
Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
December 22, 2016
SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
December 19, 2016
DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
November 15, 2016
German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
October 10, 2016
STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.
September 14, 2016
Webinar explores the impact of ISO 26262 on DFT requirements, and what is being learnt from the introduction of the standard at ON Semiconductor.
September 12, 2016
Ultra-low power security processor IP includes defences against side-channel attacks, data and instruction encryption, DSP options for sensor processing and more.
August 30, 2016
A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
August 27, 2016
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
July 12, 2016
Synopsys has introduced TetraMAX II, a faster and more parallelisable ATPG and diagnostics solution, which is now also certified for use in ISO 26262 compliant automotive designs.