Internet of Things: an opportunity, but for whom?
Building the internet of Things will demand collaboration and a healthy ecosystem
Synopsys
Synopsys adds formal, CDC, low-power checks to Verification Compiler
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
Chipmaking’s future: all of the nodes all of the time
The stall in Moore's Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.
Samsung certifies Synopsys tools, IP at 14nm
Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Synopsys uses virtual prototyping kits to kick start IP integration
Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
Synopsys adds vector DSP operations to ARC EM processor IP
Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.
IP takes center stage in push towards systems engineering
At DAC 2014, some 30 per cent of exhibitors are IP suppliers, offering design services or both, demonstrating how system-level design is about building on what has gone before.
Synopsys speeds HAPS prototyping with ProtoCompiler
HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
FinFET variability issues challenge advantages of new process
Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
Software quality acquisition to bring Synopsys “new friends”
Software quality testing company acquisition will broaden Synopsys's reach as well as serving current customers
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