Still time to get to European design and verification conference
Next week’s DVCon Europe, to be held in Munich on 14 and 15 October, is nearly upon us. We’ve already had a look at some of the program: here are links to more details.
Day one (Tuesday 14 October) hosts 14 tutorials or meetings on the following topics:
- European SystemC user group meeting
- Advanced Universal Verification Methodology (UVM)
- An Introduction to using Event-B for cyber-physical system specification and design
- Enabling energy aware system level design with UPF-based system-level power models
- Virtual prototyping using SystemC TLM-2.0
- Requirements-driven verification methodology for standards compliance
- Easier UVM – making verification methodology more productive
- The How To’s of metric driven verification to maximize verification productivity
- Creating portable tests with a graph-based test specification
- Attack your SoC power challenges with virtual prototyping
- Algorithm verification with open source and SystemVerilog
- Revolutionary debug techniques to improve verification productivity
- Architecting your UVM testbench for simulation/ acceleration reuse to enable block to system verification productivity
- Extending proven digital verification techniques for mixed-signal SoCs with VCS AMS
Day two (Wednesday 15 October) starts with a keynote from Bernd Adler, wireless CTO and division vice president of Intel Mobile Communications, entitled “Tomorrow’s Smart Mobile Systems – by the Power of Ten.”
The technical program that follows covers presentations and a poster session in the following areas:
- Analog/mixed-signal design and verification
- Advanced verification
- IP reuse & design automation
- System level design & verification
- Low power methodologies
- Verification management
DVCon Europe also hosts an exhibition, and plenty of opportunities to network with fellow engineers, EDA tool company representatives, training institutes and service providers.
Registration is still open here.
