EDA

National Instruments wants to shift the focus for many embedded systems designers away from hardware cost optimization towards graphical programming as a way of reducing the time it takes to get targets up, running and productive.

Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.

Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.

HAPS-70 boards launch with latest Xilinx chips, high-speed time-domain multiplexing and Synopsys' take on the debug crunch.

You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.

The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.

Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.

How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.