November 27, 2012
Cadence Design Systems has developed semiconductor IP for the automotive industry's OPEN Alliance to make ethernet the core networking backbone of future motor vehicles.
November 26, 2012
National Instruments wants to shift the focus for many embedded systems designers away from hardware cost optimization towards graphical programming as a way of reducing the time it takes to get targets up, running and productive.
November 19, 2012
Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.
November 16, 2012
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
November 16, 2012
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
November 13, 2012
Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.
November 12, 2012
HAPS-70 boards launch with latest Xilinx chips, high-speed time-domain multiplexing and Synopsys' take on the debug crunch.
October 30, 2012
You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
October 26, 2012
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
October 25, 2012
Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.