Aart de Geus on the changing face of EDA
The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.
EDA
DAC 2012: Synopsys marries virtual and FPGA prototyping
Expose your transaction-level innovations to the real world early on and catch bugs before simulation.
DAC 2012: A look inside Accellera’s UCIS
Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.
DAC2012: Blue Pearl partners Xilinx, develops grey-box approach to ARM cores
Blue Pearl is building alliances to bring its timing analysis tools to more users.
DAC 2012: STMicro, Cadence, GlobalFoundries in 20nm AMS claims
The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.
DAC 2012: Atrenta to automate production of power-intent constraints
Atrenta is updating existing tools and planning new ones to help designers get the most bang for their joule.
DAC 2012: Calypto brings tools together for high-level power savings
Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.
DAC 2012: Introducing Flexras Technologies
French start-up and conference debutant joins the drive to ease partitioning for FPGA prototypes
Making dummy fill smarter
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Cadence joins the dots for verification
The EDA giant has accelerated and integrated its tool suites and broadened its verification IP catalog in its new look System Development Suite.