EDA

The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.

Expose your transaction-level innovations to the real world early on and catch bugs before simulation.

Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.

Blue Pearl is building alliances to bring its timing analysis tools to more users.

The troops will be out in force next week to claim progress on 20nm AMS design flows that take manufacturability into account.

Atrenta is updating existing tools and planning new ones to help designers get the most bang for their joule.

Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.

French start-up and conference debutant joins the drive to ease partitioning for FPGA prototypes

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.

The EDA giant has accelerated and integrated its tool suites and broadened its verification IP catalog in its new look System Development Suite.