Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and techniques incorporated from place-and-route to try to put into reverse the explosion in time it takes to get an SoC from layout to tapeout.
Tempus is a response to the growth in number of timing views that design teams have seen over the past decade caused by a combination of nanometre-process effects and the need to support many different power modes to save energy.
“Low power is important across all markets and we are seeing more design complexity. The number of modes that have to be analyzed is increasing. As a result the time taken for design closure is increasing. Timing signoff is taking as much as 40 per cent of the implementation flow at 20nm,” said Anirudh Devgan, corporate vice president for silicon signoff and verification in Cadence’s silicon realization group.
The current problem with signoff is that the iterations needed to make a design close timing have become increasingly onerous, partly because the analyses and fixes remain decoupled. The Tempus tool brings in optimizations from the company’s Encounter suite to fix violations within the timing tool itself rather than forcing them to be done as ECOs in the implementation tools for the fixes then to be re-analyzed within the timing tool to check that they perform as expected, which is not always the case.
“We can do design closure activities that used to take two to three weeks previously in a few days using Tempus,” said Devgan.
As well as performing fixes, Tempus introduces two techniques. One is to reduce the amount of time it takes to generate the views themselves.
“There already was some parallelism using in timing analysis, but these designs are huge. So the parallelism required is massive parallelism,” Devgan said. “We can share memory across multiple machines. The way that the parallelism is achieved, it runs well across machines interconnected by 1Gb/s Ethernet and they do not need to be very high performance. There are a lot of cheap machines already used in simulation farms that have 128Gbyte of memory each that run well with Tempus, so users can reuse that resource for faster timing closure.
“We have seen a 10x performance improvement through parallelization,” Devgan added.
The second change is the introduction of path-based analysis to improve the overall accuracy of timing, particularly for critical paths. Excessive guardbanding using traditional graph-based approaches has made it difficult to close timing for critical paths. Path-based techniques make it possible to claw back performance. Devgan said the path-based algorithms are, on average, 3 per cent more accurate than existing techniques.
“That 3 per cent can be used to close timing more quickly or used to recover power,” Devgan claimed.
Path-based analysis is more compute intensive than graph-based but improved algorithms to ensure that the correct paths are analyzed and the addiitonal of massive parallelism makes it feasible now, according to Cadence.
“The typical workflow would be to run graph-based analysis first and then run path-based on the critical paths,” Devgan explained.
Sanjive Agarwala, director of processor development at Texas Instruments, said: “As we move to more advanced process nodes, timing closure becomes more difficult. It’s great to see Cadence taking on this challenge by offering new technology designed to tackle tough design closure issues.”