Forte Cynthesizer aims at performance, power and ease of use

By Paul Dempsey |  No Comments  |  Posted: May 14, 2013
Topics/Categories: Blog - EDA, - ESL/SystemC  |  Tags: , , ,  | Organizations:

Forte Design Systems‘ Cynthesizer 5 edition of its high-level synthesis tool is released this quarter with across-the-board enhancements for low power, faster performance and some SystemC hand-holding to promote ESL abstraction (though we do wonder how many of you haven’t got the message yet).

So, as the new launch provides evidence that the pre-DAC announcement flow is building, here are the key points.

  • Power: Forte is adding three new tuning knobs for optimization across datapaths, registers, clock trees and memory.
  • Architecture: The company has developed a new one for its synthesis core that combines scheduling and allocation for enhanced performance.
  • SystemC: An updated Cynthesizer IDE is aimed at both advanced and newbie users, and also includes ‘kick-starters’, essentially pre-defined templates that users tweak according to their requirements.

Here’s a little more on each in turn.


There’s more and more discussion of taking power optimization up to the system level. As Forte themselves point out, “you can automate complex low power optimizations often difficult or impossible to realize with hand-written RTL code.”

Moreover at DATE, Docea Power talked about the rise of the power architect, a design manager working at the architectural level to define goals, set constraints and introduce enhancements as early as possible. Forte also wants his or her attention. So, how are they tugging your coat?

Specifically, the three new Cynthesizer 5 optimization knobs are:

  1. HLS-optimized clock gating to analyze microarchitectures and identify optimization opportunities that would not be self-evident in RTL.
  2. Finite state machine optimization to minimize power there and also that consumed by false switching in the datapath.
  3. Memory-targeted features to optimize accesses for performance or power.

We’re waiting on some customer stories here, but Forte says the combination of the three features can deliver power reductions of up to 60%.

Cynthesizer Architecture

Forte is obviously leveraging both performance and result benefits by now combining scheduling and allocation within the latest C5 synthesis core.

Part of that includes a new raft of scheduling algorithms aimed at speeding up the architectural analysis and delivering optimization options for the appropriate combination of power, performance and area.

On area specifically, Forte says Cynthesizer 5 typically delivers a 9% improvement against previous releases.

Again, it will be interesting to hear a bit more about how this has played out during beta.


No-one could question how hard Forte has banged the drum on ESL and SystemC. For years.

But there is still a gap between, say, Asia (particularly Japan) and Europe on one side, and North America on the other in terms of adoption. It isn’t the yawning gulf it once was, but it’s still there.

So, the Cynthesizer 5 enhancements aimed at making SystemC easier-to-use are worth noting. Its SystemC IDE is specifically aimed at all levels of expertise. But beyond that, it’s the templates that catch your interest.

We’re already seeing much the same in, say, virtual prototyping, where Synopsys provides similar building blocks within its Virtualizer environments. They sell the concept to newer (or more conservative) adopters. Meanwhile, for those already familiar with ESL, they take away much of the early-stage drudgery and allow them to get started earlier on optimization and differentiation.

Beyond that, Forte says that the Cynthesizer Workbench has been redesigned to allow faster design, debug, and analysis of SystemC models and the resulting RTL designs. The analysis environment includes SystemC and RTL source linking, waveforms, and other tools to optimize design results.

Overall, the Cynthesizer 5 launch is eye-catching because it seems well in tune with where the market is heading and what it wants. Simplification and modularization of ESL makes a lot of sense, saving time and selling the possibilities. System-level power analysis is gaining traction fast. And, of course, Forte says it’s made what the tools already do faster and better.

The real proof will come with the demos. These start at DAC in Austin and, if attending, you can request one.

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