Efforts to develop a full RTL sign-off flow took a step forward today as Real Intent signed a deal with DeFacTo Technologies, to include their respective clock-domain crossing (CDC) and design for test (DFT) tools in a combined RTL sign-off flow.
The flow integrates DeFacTo’s SIGNOFF DFT tool with Real Intent’s Meridian CDC.
SIGNOFF makes it possible to do DFT analysis and enhancements earlier in the design process, at the block, IP core, and top levels of the chip’s hierarchy. It can also be used to explore DFT strategies such as test compression, memory/logic BIST and JTAG.
Meridian CDC uses structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASICs or FPGAs are received reliably. The company says the tool can handle designs of more than 500 million gates.
Hamed Emami, vice president of worldwide sales at Real Intent, said in a statement, “DeFacTo offers unique technology for testability sign-off at the pre-synthesis stage of design. By partnering with DeFacTo, we bring design teams the best platforms in the market for RTL sign-off for both DFT and CDC issues.”
Dr. Chouki Aktouf, founder, president and CEO of DeFacTo, added, “Our collaboration with Real Intent is a natural outcome of our complementary product offerings that help eliminate complex failure modes of SoCs at the RTL stage of design.”
The joint flow will be on show in DeFacTo’s booth (#409) and Real Intent’s booth (#1031) at the Design Automation Conference, in Austin, Texas, next month.