Group to build CCIX accelerator test chip

By Chris Edwards |  No Comments  |  Posted: September 12, 2017
Topics/Categories: Blog - EDA, IP  |  Tags: , , , ,  | Organizations: , , ,

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the Cache Coherent Interconnect for Accelerators (CCIX) project. The test chip is designed to demonstrate how many-core ARM processors can work with programmable-logic accelerators in high-performance servers.

The test chip will be built on TSMC’s 7nm FinFET process node and will include a number of ARM DynamIQ processor cores sharing access to memory and peripherals using the CMN-600 coherent on-chip bus. Cadence is provide I/O, memory, and PCIExpress IP plus as well as the CCIX interface, which will connect to Xilinx Virtex FPGAs.

Babu Mandava, senior vice president and general manager of Cadence’s system-IP group, said: “The CCIX industry standard will help drive the next generation of interconnect that provides the high-performance cache coherency that the market is demanding.”

“Artificial intelligence and deep learning will significantly impact industries including media, consumer electronics and healthcare,” said Cliff Hou, TSMC vice president for R&D and technology platforms.

Noel Hurley, vice president and general manager for ARM’s infrastructure group, said: “The test chip will not only demonstrate how the latest ARM technology with coherent multichip accelerators can scale across the data centre, but reinforces our commitment to solving the challenge of accessing data quickly and easily. This innovative and collaborative approach to coherent memory is a significant step forward in delivering high-performance, efficient data centre platforms.”

The CCIX project is one of three separate initiatives aimed at providing high-speed interfaces between manycore SoCs and accelerators. Gen-Z focuses on memory-centric architectures and OpenCAPI was derived from IBM’s work on accelerators for the Power architecture.

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