Mentor targets next-gen Ethernet with emulation
Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.
Archives
IMEC 5nm test chip to explore EUV and SAQP litho options
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
Software puts deep learning onto embedded DSP
Ceva has launched a software package intended to streamline the porting of convolutional neural network implementations to the XM4 DSP core.
Tensilica vision processor cuts power through memory changes
Memory efficiency has driven the design of the latest video and image processor core developed by Cadence Tensilica.
Samsung taps Mentor tools for higher yielding close-loop DFM
Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
Menta aims for TSMC 28nm with embedded FPGA cores
Menta has launched a family of off-the-shelf IP cores aimed at TSMC’s 28nm processes to provide reconfigurability for SoCs.
Debug monitors look for deadlock
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
Samsung applies early prediction and color management to 10nm plans
Rapid virtual prototyping and a metal stack that's more designer friendly are two of the ways in which Samsung aims to build up foundry market share for its 14nm and 10nm finFET processes.
PSpice builds interfaces to PCB and system-level cosimulation
The need for virtual prototyping at the PCB-design has led to changes in the way PSpice is being used – with much greater emphasis on cosimulation.
GlobalFoundries tunes 28nm for smaller, lower-power FD-SOI
GlobalFoundries has developed variants of the 28nm FD-SOI process that offer smaller die sizes and lower-power operation.