Archives

The Calibre vendor will have a strong technical presence at the leading lithography conference taking place in late February in San Jose.

Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.

The Multicore Association has started work on standardizing a set of APIs that aim to simplify communications between processors in heterogeneous multicore SoCs

HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.

The Qt Company has changed the licenses it supports on the open-source versions of its user-interface software framework, removing the LGPL2.1 version.

The Prpl Foundation has published a guide to techniques it claims will improve the security of embedded systems.

According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.

Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability

Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.

Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.