OneSpin brings formal to bear on ISO 26262 fault tracing
OneSpin Solutions has used its formal-verification technology as the basis for an app intended for ISO 26262 projects that analyzes the ability of a design to deal with fault conditions.
Archives
Docea adds API to model power software interactions
Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to show how chipset designs would fare under a variety of software-based power-management algorithms.
Intelligent software testing conference coming up online – and in Bristol
Online conference discusses software testing for avionics and security, code coverage, agile methodologies, behaviour-driven development and more
SRAM IP “halves dynamic power” on 28nm FDSOI
Embedded SRAM IP said to reduce dynamic, static power on FDSOI at cost of extra 10% area
DAC2015: Real Intent at the Design Automation Conference
Real Intent has lined up a mixture of technology and speed tests for its presence on Booth #1422 at the Design Automation Conference this year.
DAC 2015: Cadence Design Systems at the Design Automation Conference
An overview of Cadence's activities at DAC and a last-minute call-out if you want to register for its breakfast and luncheon sessions.
DAC 2015: Mentor Graphics at the Design Automation Conference
Review highlights from Mentor's activities at DAC and grab your last chance to register for in-depth technical sessions.
COMPUTEX 2015: Qualcomm edges Intel out of UK smartwatch start-up
Blocks' promo video says its work was 'Funded by Intel' but Qualcomm has announced that the modular watch company will be using its Snapdragon 400.
COMPUTEX 2015: Acer founder urges Taiwan to shift focus to software
Stan Shih says the Internet of Things is forcing Taiwan to reconsider its traditional concentration on electronics hardware.
Cadence deploys parallel strategy for faster synthesis
RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.