PSpice builds interfaces to PCB and system-level cosimulation
The use of digitally assisted analog and interactions between embedded software and analog I/O is driving changes in the way that Spice is being used at the PCB level. Virtual prototyping is being used more heavily, leading to changes in the way that tools such as Cadence Design Systems’ PSpice are being deployed and used.
“We noticed from customers in the PCB world that there has been a significant change,” says Parag Choudhary, engineering architect and product engineer in Cadence’s silicon package and board division. “Technology was stable for a long time but concerns over speed and power are changing things. Things are also changing because hardware prototyping has become extremely expensive. People want a solution that lets them do a couple of levels of analysis up front before going to hardware.”
A further reason for virtual prototyping at the PCB level is the greater interaction between support circuitry and the larger SoCs on a board, leading to a high degree of software control being exercised over functions such as power delivery.
“There are mixed-signal control loops that you can only do with embedded software. Traditionally, in power control you might see one device every few years. We are now seeing a lot of innovation on power devices,” Choudhary explains, noting that tools such as MathWorks are used to develop the algorithms that are then converted into a combination of C and Spice models.
“We looked at the flow and how designers could model blocks with software. Cosimulation has been there for some time but used mainly for top-down design. Traditional approaches using Spice were not working out. So, we have provided a bottom-up architecture that lets every block within the design be cosimulated while keeping the interfaces accurate.”
One step was to make it easier to inspect Spice netlists that need to be incorporated into a PCB-design environment. “Then on the PSpice side, we made it possible to have embedded models inside the digital simulator. Each block can be cosimulated at different levels. You can take a mixed-signal block and accelerate simulation using different forms of model, such as timed and untimed. You can ensure that I/O is handled with the right accuracy. We can take the entire PCB and take it into a simulation.
“One could be a SystemC block, or a C-level block, or pick up fast model from ARM. You can put in PSpice models into the block and get mixed-signal results out. Everything is brought together and simulated at the PCB level,” Choudhary says.
One issue with building chip-level models into full PCB simulations is one of model availability. “IC companies are very sensitive about their models. Even though they often have their own detailed models, they don’t like to give those models away. They try to simplify the model to hide the IP,” Choudhary explains. “We provide an interface that turns Verilog-A models into compiled model that can run as-is within PSpice. You are able to protect the IP and give the customer a more accurate model.”
A lot of basic functions will not have models provided by vendors. What Cadence has done with PSpice is build a number of models for generic subcircuits, such as VCOs, PWM generators and components such as LEDs that can be pulled as ready-made parts into a design, given appropriate parameters and simulated.
“Spice has a diode model but it’s a challenge for people to pick one up and make LED out of it. You have to set certain parameters to make it an LED such as doping factor. With the LED model, if you have the data sheet and the device parameters, you can just enter those to get the relevant Spice model.”
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