Debug monitors look for deadlock
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework, aiming to provide a way of picking up bus-contention problems without the need to stream out large amounts of trace data.
“Our customers tell us that intermittent deadlock and stall conditions are amongst the hardest problems to solve in their SoC designs,” said Gadge Panesar, UltraSoC CTO. “These conditions are a major contributor to the current crisis in the SoC industry. Conventional approaches either ignore the problem, or attempt to deal with it by generating massive, unmanageable data sets. UltraSoC takes a smarter approach.”
The UltraSoC approach uses a watchog-style approach, deploying a protocol-aware on-chip bus monitor that triggers when the time taken for a bus transaction exceeds a programmable limit. When it spots by a deadlocked transaction, the system provides the culprit’s transaction ID and address over the debug port, guiding the engineer’s attention to both the master and slave of the problem.
A similar approach is used for software deadlocks, often triggered by two tasks accessing shared resources such as hardware peripherals or queues and mailboxes used for interprocess communications. A typical example is where two tasks each have control over a resource the other needs and neither can complete until it obtains the other.
In this case UltraSoC provides an on-chip status monitor which can be used to detect the fault condition, halt the processors and initiate data capture to isolate the problem.
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