France-based programmable-logic IP core specialist Menta SAS has launched a family of off-the-shelf IP cores aimed at TSMC’s 28nm processes to provide a degree of reconfigurability for SoCs.
The IP core allows an FPGA fabric to be embedded in an SoC for the implementation of customer-specific features or to support changes to an evolving standard.
The family of IP cores includes six embedded FPGA options that have from 4000 to 60,000 equivalent ASIC gates together with digital signal processing (DSP) blocks. The IP cores are delivered as hard macros of logic, custom-circuitry, and memory blocks that can be customized in type, number, and size. The eFPGA IP cores are designed for compatibility with common ASIC and SoC test-generation tools, supporting fault coverage up to 99.8 per cent.
The IP cores are supplied with a toolset that supports design from HDL synthesis to mapping, place and route and programming-bitstream generation.