Speed boost for Palladium emulators

By Chris Edwards |  No Comments  |  Posted: September 10, 2013
Topics/Categories: Blog - EDA  |  Tags: , , , ,  | Organizations:

Cadence Design Systems has upgraded the core processors and updated the software for its Palladium emulators to provide a total capacity of some 2.3 billion ASIC gates and improve performance, particularly for system-level tests.

Frank Schirrmeister, senior director at Cadence, said: “There are not many designs that need 2.3 billion gates out there but we have at least the bragging rights with Palladium XP II. We have also have approximately 50 per cent higher performance.”

Since introducing the concept of in-circuit acceleration, which allows the unit to be partitioned into smaller sections and use to speed up smaller simulations, down to around 4 million gates apiece, Cadence has increased the number of simultaneous users to 512. “This is one of the key advantages over an FPGA array. It’s why we call it a verification-computing platform,” said Schirrmeister. “You can really use it as a multiuser system.”

Through the use of a host-based transaction-modelling capability introduced with the latest generation of software, the speed at which an operating system can be booted has been boosted by up to 60 times. Once the system has booted, the processor can continue on the host using a transaction-level model with peripherals and accelerators running on the Palladium for a performance improvement of about ten times that of traditional emulator-based setups.

To support power analysis, Schirrmeister said the unit can provide toggle information more quickly and it will support hierarchical CPF for power intent.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors