Accellera Systems Initiative has created a working group to look at one of the knottiest problems in IC design: to simplify the job of checking designs when the bits come from so many sources and use languages that were not built for interoperability.
The Multi-Language Working Group (MLWG) has been formed to create a standard and functional reference to improve interoperability between components in a multi-language verification environment. The working group aims to build a reference implementation and also look at ways to bring concepts from the Universal Verification Methodology (UVM) to environments and languages that come from legacy projects.
Shishpal Rawat, chair of Accellera, said: “This is a natural extension of a universal verification methodology by which legacy verification IP can be used natively. It preserves the industry’s investment in verification IP for modules that have already been designed and verified in non-native simulation environments. It alleviates the need for redeveloping verification IP and allows development teams to focus on verification IP for new IP modules.”