DAC 2013 Preview VII: Verification and simulation

By Paul Dempsey |  No Comments  |  Posted: May 22, 2013
Topics/Categories: Blog - EDA  |  Tags: , , ,

DAC 2013’s technical program has four sessions on verification clustered on Wednesday and Thursday. With an increasing number of companies augmenting their tool flows with in-house enhancements targeting emerging challenges and various bottlenecks, they are likely to be very busy.

These are some of the papers that caught our attention in the different sessions.

DAC 2013 Session 24: Secrets of Analog Verification

Wednesday, June 5,  9:00am-10:30am, Room:  13AB

ABCD-L: Approximating Continuous Linear Systems Using Boolean Models (24.1)

This research from UC Berkeley, also a ‘Best Paper’ candidate, tries to leverage familiar technology to new effect. It describes a way to use existing Boolean system verification techniques in the analog domain to model continuous linear systems.

Other papers in the session explore the use of Bayesian frameworks for data correlation, machine learning and hybrid reachability in the context of digitally intensive analog circuits.

DAC 2013 Session 31: Accelerated Simulation and Verification for Power Grid and Memory

Wednesday, June 5,  1:30pm-3:00pm, Room  14

Scalable Vectorless Power Grid Current Integrity Verification (31.1)
Constraint Abstraction for Vectorless Power Grid Verification (31.2)

The session organizers identify vectorless verification as one technique that could ease the flow for power networks by removing much of the need for explicit simulation. Two papers, from the Illinois Institute of Technology and the University of Minnesota respectively, outline different strategies.

Other papers consider verification techniques for electromigration in copper interconnects and the implementation of a highly efficient ‘TinySPICE’ for graphics processors.

DAC 2013 Session 39: Verification: from SystemC to the Reality of Silicon

Wednesday, June 5, 4:00pm-6:00pm, Room: 15

Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation (39.1)
Handling Design and Implementation Optimizations in Equivalence Checking for Behavioral Synthesis (39.2)
A Counterexample-Guided Interpolant Generation Algorithm for SAT-based Model Checking (39.3)
A Robust Constraint Solving Framework for Multiple Constraint Sets in Constrained Random Verification (39.4)
Simulation Knowledge Extraction and Reuse in Constrained Random Processor Verification  (39.5)
Hardware-Efficient On-Chip Generation of Time-Extensive Constrained-Random Sequences for In-System Validation (39.6)

There isn’t really one paper – or even two – that sets the tone for Session 39. Rather, it cuts a broad swathe from high levels of abstraction right through to post-silicon verification, highlighting various formal and simulation-based strategies. Obviously, some attendees may cherry-pick from the offerings. However, there’s equally no harm in taking the holistic view.

Contributors are the University of Bremen, Portland State University/University of Texas, National Taiwan University (two papers), UC Santa Barbara/Freescale Semiconductor, and McMaster University.

DAC 2013 Session 59: Got Yield Problems? Take a Closer Look at Variability and Reliability!

Thursday, June 6, 3:30pm-5:30pm, Room: 15

On the Potential of 3D Integration of Inductive DC-DC Converter for High-Performance Power Delivery (59.1)
Full-Chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs (59.2)
An Accurate Semi-Analytical Framework for Full-Chip TSV-Induced Stress Modeling (59.3)

3D is coming and three papers in DAC 2013’s final verification session look at its potential impact. The first, from GeorgiaTech, looks at the an efficient form of power delivery for a 3D stack using a dedicated DC-DC tier. The second and third, from respectively GeorgiaTech again and UTexas-Austin, address critical challenges posed by through-silicon-vias.

Further papers address existing techniques and challenges including computational innovation for statistical static timing analysis, timing in logic synthesis, and the manipulation of variation to a design’s advantage through the use of unclonable circuits.

Catch up with our earlier DAC previews at these links:

DAC 2013 Preview I: Putting users first and marking 50 years

DAC 2013 Preview II: Panels

DAC 2013 Preview III: Embedded

DAC 2013 Preview IV: Management and Training Days

DAC 2013 Preview V: Rounding out the keynotes

DAC 2013 Preview VI: CEO ‘visions’ added

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