Mentor Graphics is working on technology to analyze the effects of mechanical stress on integrated circuits, describing progress at the company’s U2U conference in San Jose this week (April 21).
The development of Project Glacier is a response to the “increased use of thinned substrates”, said Michael White, director of product marketing in Mentor Graphics’ design-to-silicon division. “As you thin a die, it can start to bend like a potato chip. It creates chip-package integration issues.”
“We’ve developed some technologies in Mentor for the analysis of unexpected chip-package integration issues. Glacier is delivered as IP and is being used by a big customer. We are interested in finding other partners to help us create a production-worthy solution,” White said.
The simulation software, based around compact models, uses multi-scale techniques because highly localized stress sources, such as solder microbumps attached to the bottom of the die or through-silicon vias can create long-distance stresses.
“The tool needs calibration just once for a given process and foundry,” said Mentor Graphics principal engineer Valeriy Sukharev.
There are two use modes for the tool. One uses basic LEF/DEF data to produce early analysis of probable high-stress locations useful to help with floor planning – critical paths can be placed to avoid these regions. A detailed run using GDSII or Oasis data first identifies stress hotspots that can then be targeted for detailed analysis to avoid bogging the tool down in extensive calculations where stress is unlikely to be an issue.
One early-access customer found stress was causing a DAC to fail. Placed close to the edge of a die at the bottom of a stack, the DAC encountered far more substrate stress than similar blocks that were covered by other chips. The result was much lower parametric yield than expected.
“The die edge is very dangerous because the effects of thermal expansion can lead to huge changes in stress there,” said Sukharev.