The company is also bundling its new CPU and GPU cores in a premium IP platform that can be tuned for next generation applications and devices.
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
Mentor is active across the program and its main and Verification Academy booths within the exhibition in Las Vegas.
Security and machine learning are two topics that take center stage at DAC this year, says the conference’s general chair Rob Aitken.
Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.
Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
Electronic musician Thomas Dolby will be among the keynote speakers at the 56th Design Automation Conference (DAC) in Las Vegas.
An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.
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