Machine learning and chiplets headline VLSI Symposia
Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
machine learning
DAC announces first set of keynotes for 2019
Electronic musician Thomas Dolby will be among the keynote speakers at the 56th Design Automation Conference (DAC) in Las Vegas.
ODSA weighs options for chiplet interconnect
An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
Catapult HLS integrates eFPGA IP for faster development
Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.
Free registration opens for DAC
The Design Automation Conference (DAC) has kicked off free registration for the exhibit floor at early June's Las Vegas event.
China Focus 2: The Design Dilemma
Do China's ambitions as a world-class innovator face fundamental challenges as a result of the sector's existing economic infrastructure?
China Focus 1: Wally Rhines maps startup and design growth
In the first of a weekly series on China's evolving design sector, we look at how the Mentor President and CEO identifies some of the key drivers.
Safety and test IP heads for automotive AI applications
Automotive AI specialist FABU has licensed a portfolio of IP from Synopsys to help assemble ISO 26262-compliant SoCs
HPC futures report puts acceleration first
A report put together by Europe's HiPEAC high-performance computing research network argues computing is at an architectural turning point
Achronix builds machine learning IP into eFPGA
Achronix has incorporated direct support for machine learning into the latest version of its eFPGA architecture.
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