Synopsys introduces fast full-chip yield analysis and optimization tool
Synopsys has released PrimeYield, a tool for analysing and optimizing the yield of a design before it is made. The company claims that its combination of fast statistical methods and machine-learning strategies makes it between 100 and 1000 times faster than alternatives, depending on the use case. It says the tool will work on system-on-chip (SoC) designs with billions of transistors.
Among the key claims for the tool is that its patented full-chip-scale parametric design yield analysis will give accurate statistical yields with over one thousand times faster performance than a Monte Carlo based static-timing analysis. The company also says the tool’s intelligent path simulation with HSPICE accuracy will run between one hundred and one thousand times faster than a traditional Monte Carlo simulation.
“The ability to identify and fix yield hotspots during the pre-silicon design phase is a game-changer,” said Dan Hutcheson, chief executive officer and chairman at VLSI Research. “Shifting-left design yield optimization before trial production without the need for a full Monte Carlo statistical simulation significantly lowers non-recurring engineering cost, improves productivity, and, more importantly, shortens the time-to-money for a new design.”
PrimeYield’s fast statistical engine uses the core engines of Synopsys’ gold-standard PrimeTime sign-off and HSPICE simulation tools. This helps speed up the yield analysis and optimization process to the point at which it can be applied to large chips within turnaround times that fit today’s pressured design timelines.
PrimeYield uses machine-learning strategies to performs fast Monte Carlo statistical simulation on critical timing paths with HSPICE accuracy. Its patented parametric yield analysis with statistical correlation modelling enables statistics-based yield analysis and optimization on large-scale SoCs with billions of cells, something previously only feasible for a few dozen cells.
PrimeYield can rapidly identify and drive optimization of yield-impacting cells caused by statistical correlations or sensitivity to design variations such as supply voltage drops or manufacturing variability. It uses industry-standard inputs, and so can be deployed quickly.
PrimeYield will sit alongside Synopsys’ Yield Explorer post-silicon yield analysis and management tool.
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