DAC returns to San Francisco in July for its 59th year as a purely in-person event.
Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.
Arm has used machine-learning tools supplied by the Solido group at Siemens Digital Industries Software to speed up IP validation runtime a thousand-fold compared to conventional statistical methods.
The program for the 58th Design Automation Conference, which returns to a physical format in December, is online and is running its I Love DAC promotion for free access until the end of this month.
Cadence has organized its machine-learning platforms into three families intended to cover a wide range of on-device AI applications.
DVCon Europe has announced its first two keynote speakers, who will cover the topics of AI and the role of virtualisation in ADAS design and implementation
Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
Xilinx has reworked its Versal FPGA for edge-AI applications.
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