DAC 2019 preview: Mentor

By TDF Staff |  No Comments  |  Posted: May 20, 2019
Topics/Categories: Blog Topics, Conferences, Blog - EDA, IP  |  Tags: , , ,  | Organizations: , , , , ,

Mentor, a Siemens business, will be present across the technical program at exhibition at the 2019 Design Automation Conference in Las Vegas next month. DAC will take place at the Las Vegas Convention Center from June 2-6 (Exhibition: June 3-5), and Mentor will have two booths: a main one (#334) hosting suite sessions and networking; and its eponymously focused Verification Academy (#617).

Here are some of the highlights, but you can also find out more about Mentor at DAC and register for its events the company’s dedicated DAC webpage.

Main conference

DAC Pavilion (Booth #871)

Fundamental Shifts in the Electronics Ecosystem

Monday June 03, 10:30am – 11:15am

Wally Rhines, CEO Emeritus of Mentor, a Siemens business, will examine major new market opportunities like AI/ML, automotive, 5G, etc. and how these markets will call for new design activity and the need for broader design tool innovation. He will also explore whether we are heading into a period of stability after three years of disruption or if the revolution will continue.

Straight Talk with Tony Hemmelgarn

Monday June 03, 11:30am – 12:00pm

Tony Hemmelgarn, CEO of Siemens Digital Industries Software, will join editor Ed Sperling for a wide ranging one-to-one discussion – including, no doubt, more about how Mentor and EDA are being integrated within Siemens broader digital twin-led offering for design and product enablement.

Myth vs. Reality: What 5G is Supposed to Be, And What it Will Take To Get There

Tuesday June 04, 11:30am – 12:00pm

Neill Mullinger of Mentor joins colleagues Peter Zhang of Synopsys and Ian Dennison of Cadence Design Systems to look at some of the design challenges surrounding 5G – for example, the signals do not travel far nor easily penetrate many solid objections – and what novel strategies are needed to address them.

Technical papers

All papers are listed by date, session number and title. Full details on where to attend them can be found by following the integrated links.

Monday June 3

4.4 Electromigration Signoff based on IR-drop Degradation Assessment

8.4 Local Layout Effect Aware Design Methodology for Performance Boost below 10nm FinFET Technology

Tuesday June 4

18.4 A Lightweight Hardware Architecture for IoT Encryption Algorithm

Wednesday June 5

56.1 Moving Up in the World

66.4 Virtual Methodology For Performance and Power Analysis of AI/ML SoC Using Emulation

69.4 Efficient Verification of High-level Synthesis IP


Details on when an where poster papers can be viewed can be found by clicking on the relevant link.

123.21 Metric Driven Power Regression – A Methodology based Metric Driven Approach for Power Regressions

123.25 River Fishing: Leverage Simulation Coverage to Drive Formal Bug Hunting

124.2 Comprehensive Analog Layout Constraint Verification for Matching Devices

124.7 Enabling Exhaustive Reset Verification in Intel Design

124.16 A Smart RTL Linting Tool with Auto-correction

124.25 Configurable Multi-protocol AUTOSAR-based Secure Communication Accelerator

125.12 Faster PV Signoff Convergence in P&R using RTD

125.14 Hybrid Methodology- An Innovative Methodology for Hierarchical CDC Verification

125.17 Functional Safety on A-R-M CPUs

125.21 Tackling the Increasing Challenge of IR drop & EM Fails in Advanced Technologies with a Push Button Solution

Exhibit floor

The main Mentor booth (#334) can be found at the west end of the exhibit floor, and, alongside technical sessions, will also host panels and networking events. Coffee is on offer from 9:00am-2:00pm, followed by Happy Hour from 3:45pm-4:45pm. Verifications events – including sessions on Portable Stimulus and UVM – will also take place at the Verification Academy booth (#617).

The technical sessions at the main booth will cover these areas:

  • AMS Verification
  • Analog/Mixed-Signal Verification
  • Design & functional Verification
  • Digital Design & Implementation
  • IC Design & Test

A full list and pre-registration is available here.

Expert panels

These panels coinciding with the Happy Hour event at the main Mentor booth on Monday and Tuesday from 4:00pm–4:45pm.

Monday June 3

Design Smarter Innovations Faster using AI/ML and More with Mentor, a Siemens Business

Experts from various Mentor divisions will discuss how artificial intelligence and machine learning technologies are being applied across the company’s tools.

Speakers: Ellie Burns, director of marketing, Calypto Systems Division; Vijay Chobisa, product marketing director, Mentor Emulation Division; Geir Eide, product marketing director, D2S Tessent Division; Amit Gupta, general manager, Solido, IC Verification Solutions Division; and Steffen Schulz, vice president product management, D2S Calibre Marketing

Tuesday June 4

Functional Safety in Isolation – Can Safety Be Collaborative?

Representatives from three leading players in the automotive sector will discuss how to address what is already one of the greatest design challenges, and one that is expected to increase in complexity and scope as the market strives toward Level-5 vehicle autonomy.

Speakers: Yves Renard, Functional Safety Manager, ON Semi; Ghani Kanawati, Technical Directory of Functional Safety, Arm; and Matt Blazy-winning, Functional Safety Director, NXP.

And finally….

Don’t miss out on the opportunity to pick up a copy of the new book by Wally Rhines,, From Wild West to Modern Life, during signing sessions on Monday at 5:00pm and Tuesday at 10:00am at the Mentor booth.

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