machine learning

May 23, 2019

AI and ML fuel Catapult and Calibre updates

Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
May 21, 2019

Achronix deploys network on chip for faster FPGAs

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
Article  |  Topics: Blog - IP, PCB  |  Tags: , , , , , , , ,   |  Organizations:
May 20, 2019

DAC 2019 preview: Mentor

Mentor is active across the program and its main and Verification Academy booths within the exhibition in Las Vegas.
May 13, 2019

Security, machine learning, and variety at DAC

Security and machine learning are two topics that take center stage at DAC this year, says the conference’s general chair Rob Aitken.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations: , ,
May 8, 2019

Formal engines learn from experience

Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: ,
April 22, 2019

Machine learning and chiplets headline VLSI Symposia

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: , ,
April 9, 2019

DAC announces first set of keynotes for 2019

Electronic musician Thomas Dolby will be among the keynote speakers at the 56th Design Automation Conference (DAC) in Las Vegas.
April 4, 2019

ODSA weighs options for chiplet interconnect

An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
April 2, 2019

Catapult HLS integrates eFPGA IP for faster development

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.
Article  |  Topics: Blog - EDA, - HLS, Blog - IP  |  Tags: , , , , ,   |  Organizations: ,
March 12, 2019

Free registration opens for DAC

The Design Automation Conference (DAC) has kicked off free registration for the exhibit floor at early June's Las Vegas event.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors