Keynotes for DVCon Europe announced
DVCon Europe has announced its first two keynote speakers, who will cover the topics of AI and the role of virtualisation in ADAS design and implementation
machine learning
Cadence uses reinforcement learning to tune flow
Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
AI’s design speedups, with and without machine learning
At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
Xilinx retools Versal for high-end edge AI
Xilinx has reworked its Versal FPGA for edge-AI applications.
PCIe 6.0 gets verification IP as formal arrival approaches
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Siemens extends Solido’s reach into IP validation with Fractal
Latest acquisition adds technologies to mitigate rising verification time and cost for third-party IP.
Edge AI focuses on power efficiency at Linley Spring
The Linley Spring Conference saw several vendors present architectures that they claim can deliver more performance to edge systems than what are now traditional approaches.
Arm looks to explore new realms for security with v9
Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.
Tessent Streaming Scan Network to shrink SoC test writing and runtimes
Mentor's latest additions to Tessent aim to cut test time by a factor of four but remains tailored for increasing design complexity.
DVCon keynoters look to software for verification optimization ideas
Speakers at this year's DVCon Europe called on the hardware community to find inspiration in software-development trends.
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