A contribution from software-parallelization specialist Silexica is helping to update the Multicore Association’s Software/Hardware Interface for Multicore/Manycore (SHIM) standard.
Version 1.0 of SHIM, which launched in 2015, is a specification that helps software tools decide useful ways to partition software across multiple cores and accelerators. SHIM provides a machine-readable way of building architectural descriptions to help software design, analogous to the IP-XACT format used in hardware design.
Architectural features that SHIM describes include processor cores, accelerators, memory arrays, caches, and inter-core communication channels. The specification lets SoC makers provide details on instruction and communications speed and behavior. The metrics can be used for performance estimation, system configuration, and hardware modeling.
The initial updates to be included in SHIM 2.0 will come from Silexica, an MCA member. Maximilian Odendahl, CEO of Silexica, said: “Silexica has a lot of experience in abstract hardware modeling, reflected in its own automated software modeling tool for multicore software developers and hardware/software system architects. As a result, we have determined that the SHIM 2.0 should include enhanced capabilities for improved performance estimation accuracy.”
Odendahl said the standard will be able to model processors that have heterogeneous functional units and single-instruction, multiple-data (SIMD) cores. It will cater for modeling pipelining effects and differences in data widths. He claimed these capabilities will allow the description of complex DSPs, hardware accelerators, and software-defined cores.
“SHIM 2.0 will also support more accurate modeling of power consumption, allowing the use of different voltages and frequencies associated with individual processor or clusters,” Odendahl added.
Masaki Gondo, software CTO and general manager of technology at eSOL and chair of the MCA working group responsible for SHIM, said: “After the completion of SHIM 1.0, eSOL was among the first companies to implement a product utilizing the standard. The eSOL Model-Based Parallelizer (MBP) tool estimates code execution performance based on architecture and performance information for the multi- or many-core processor to be implemented. Utilizing the XML-based SHIM, MBP automatically generates parallel code by allocating blocks that have been grouped on the basis of this information to separate cores.”
The working group aims to release SHIM 2.0 in Q3 of 2017.