power gating


May 24, 2018

Case study demonstrates 59% extra power savings for HPC

Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail
Article  |  Topics: Digital/analog implementation, Blog - EDA, - RTL  |  Tags: , , ,   |  Organizations: ,
May 18, 2015

Sonics readies fine-grained power-gating architecture

Sonics is moving into power management with an approach intended to substantially automate much of the job of building finely grained power-gated SoCs.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:

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