DesignCon 2017 preview: Mentor Graphics
DesignCon 2017 takes place from Jan 31 to Feb 2 at the Santa Clara Convention Center with its usual focus on PCB design and implementation.
Author Archives: TDF Staff
Virtual prototyping case study focuses on address mapping, clocking and QoS in DDR memory interface optimisation
Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
Webinar discusses SoC security, area, and power trade-offs
SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
White paper discusses optimising the efficiency of DDR memory subsystems
DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
Webinar focuses on Eldo RF verification of Tanner-based designs
On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.
Chinese dates set for Asia-Pacific editions of Mentor Forum
Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.
Real Intent extends Meridian Constraints for untimed paths
Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.
DAC 2016 preview: Real Intent
The functional verification specialist will discuss the latest updates to Ascent and Meridian - and offer top quality espresso at this year's conference.
DAC 2016 preview: Mentor Graphics
An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
DAC 2016 preview: Gary Smith EDA
The company's annual 'What to see' list is now available for download and highlights some of EDA's less recognized areas of innovation.