The release extends the software’s sign-off capabilities in functional analysis, data-driven debug and distributed design. New features include the functional analysis of timing exceptions needed for untimed paths in logic, including false paths and multi-cycle paths.
Real Intent is emphasizing the untimed analysis feature because it sees it filling a gap in the EDA market. Such paths require separate verification and are not validated by existing synthesis and static timing analysis tools. The company says this feature accelerates the sign-off of timing exceptions “by dramatically reducing by 50-percent the number of paths needing formal verification”.
Meridian Constraints verifies and propagates Synopsys Design Constraints (SDC) at the block-level and promotes them to the top-level of a design with the goals of delivering consistent specifications of system timing and faster design sign-off.
Daryl Kowalski, senior manager of product engineering at Real Intent, said, “Having correct and complete constraints and associated clock definitions ensures timing goals are met. Leveraging functional analysis capability with industry-leading formal analysis technology in Meridian Constraints gives users maximum confidence in the correctness of their exceptions, minimizing the risk of a re-spin due to bad exceptions that cause incorrect circuit operation.”
Meridian Constraints also includes iDebug, Real Intent’s design intent debugger and data manager. It employs a full database that captures all phases of SDC and clock domain crossing verification. It seeks to identify the root causes of issues, and minimize iterations and debug time through an easy-to-use programmable GUI.
Real Intent has released a video interview with Daryl Kowalski about SDC constraints management.
For more on the company’s activities at next month’s Design Automation Conference (June 5-9), which will include demonstrations of the new Meridian Constraints release, click here.